Logic compilers, also known as functional generators, are software tools used to create logic models, or circuit models. The model describes the mathematical or logical relationships between inputs into the model and outputs outputted from the model. The logic complier may also design the actual circuit represented by the circuit model. The resulting circuit models may be then incorporated into a system model whose performance can then be verified. Ultimately, the system model may be used to develop the actual hardware corresponding to the system model.
Due to the complexity and extensive labor involved in developing logic compilers, only compilers for developing simple circuits or circuits which use a highly repetitive pattern, such as memory compliers for generating memory arrays, are available, where only a relatively limited variety of circuits and features are available to the user.
Further, prior art logic compilers generally require the user to have a relatively detailed knowledge of the logic compiler in order to properly instruct the logic compiler to generate a desired circuit model.
Still further, in prior art compilers there is no capability for the user to obtain performance data on the specific circuit selected, where the performance data represents the expected performance of the actual circuit in silicon.
What is needed in the industry is a more efficient means to develop and verify logic compilers so that the compiler can be developed and tested without requiring extensive software and labor resources. What is also needed is an improved user interface system which enables the user to use the logic compiler in the most efficient manner.